The present invention relates to a MOS transistor having an SOI structure, and a method of manufacturing the MOS transistor.
In accordance with recent refinement of a semiconductor device, a large scale integrated circuit (LSI) with integration of five million or more transistors has been developed. Such high integration is indispensable to increase the operation speed of a parallel processor and the like, and is more and more accelerated in accordance with increase in functions of an LSI. As the number of integrated devices is increased, however, the power consumption is also increased. Therefore, there are increasing demands for decrease in the power consumption.
The most effective technique to decrease the power consumption of an LSI is reduction of a supply voltage so as to decrease a leakage voltage. In a generation with a design rule of 0.35 .mu.m through 0.5 .mu.m, a voltage of 5 V through 3 V has been conventionally adopted, but the supply voltage is expected to be further decreased. However, since the reduction of the supply voltage degrades a driving ability of a transistor, in order to compensate the degradation of the driving ability simultaneously with pursuit of the higher operation speed, scaling of a transistor is also required.
In the scaling of a transistor, reduction of the gate length has been the most significant parameter for the higher operation speed. Additionally, as a result of the reduction of the supply voltage, scaling of a threshold voltage has also become a significant problem. The threshold voltage of a silicon MOS transistor is conventionally set at approximately 0.6 V. This voltage is comparatively small as compared with the supply voltage, and hence has been scarcely changed through generations. However, when the supply voltage is decreased to, for example, approximately 1.5 V, corresponding to a voltage of one dry battery, the proportion of the threshold voltage to the supply voltage is very large. Also, the saturation current value of a transistor is in proportion to a square of a difference between the supply voltage and the threshold voltage. In view of this, the scaling of the threshold voltage is indispensable.
The threshold voltage is a significant parameter corresponding to the subthreshold characteristic of a MOS transistor, and has strong correlation with an off-leakage current. As is shown in FIG. 13, as the threshold voltage is decreased, the off-leakage current is largely increased. This is a fatal disadvantage to portable equipment, and means that the threshold voltage cannot be simply decreased. Accordingly, there is a demand for a technique to decrease the threshold voltage for the higher operation speed without increasing the off-leakage current.
As a countermeasure against this problem, an SOI (silicon on insulator) structure is regarded to be most promising.
The SOI structure has a characteristic that spread of a depletion layer from a drain diffused layer can be suppressed by forming a buried layer out of an oxide film in a silicon substrate. Therefore, an impurity concentration of a channel region in the semiconductor substrate directly below a gate electrode can be made low, resulting in increasing the gradient of the subthreshold characteristic. For example, a normal MOS transistor has a subthreshold slope, that is, an inverse of the subthreshold characteristic, of 80 mV/dec through 90 mV/dec, whereas an SOI transistor has a subthreshold slope as small as approximately 65 mV/dec. Thus, the threshold voltage can be decreased without increasing the off-leakage current in the SOI transistor.
An SOI substrate is conventionally manufactured by, for example, a SIMOX method in which oxygen is injected into a substrate so as to directly form a buried oxide film in the substrate, a wafer bonding method in which a silicon substrate and an oxide film substrate are adhered to each other.
However, the SIMOX method has problems that the injected oxygen can remain in an upper silicon layer (SOI) and that a damage such as lattice defect can be caused in crystal by the injected oxygen. The wafer bonding method is disadvantageous in difficulty in control of the thickness of the SOI film. Also, both in the SIMOX method and the wafer bonding method, a leakage current can be caused between the source and the drain due to an interfacial level occurring on the interface between the buried oxide film and the SOI film, so that the electric characteristic of the transistor can be disadvantageously degraded.
Furthermore, in a transistor using the SOI substrate, a potential breakdown is caused between the source diffused layer and the channel region due to injected holes, so that a kink phenomenon can be easily caused. Moreover, the SOI substrate itself is disadvantageously expensive.
As described so far, there are a large number of problems in realizing an LSI including an SOI substrate.